A Fast Locking Scheme for PLL Frequency Synrhesizers
نویسندگان
چکیده
Frequency synthesizers are used in a large number of time division multiplexed (TDMA) and frequency hopping wireless applications where quickly attaining frequency lock is critical. A new frequency synthesizer is described which employs a scheme for reducing lock time by a factor of two using a conventional phase locked loop architecture. Faster lock is attained by shifting the loop filter’s zero and pole corner frequencies while maintaining the PLL’s gain/phase margin characteristics.
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